Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE

被引：93
|
作者：
Studer, Christoph [1 ]
Benkeser, Christian [2 ]
Belfanti, Sandro
Huang, Quiting [2 ]
机构：
[1] ETH, CTL, CH-8092 Zurich, Switzerland
[2] ETH, Integrated Syst Lab IIS, CH-8092 Zurich, Switzerland
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2011年 / 46卷 / 01期
关键词：
ASIC implementation; low-power; LTE; parallel turbo-decoder; radix-4; 3G mobile communication; PERMUTATION POLYNOMIALS; INTERLEAVERS; CODES;
D O I：
10.1109/JSSC.2010.2075390
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoders that operate in parallel. To highlight the effectiveness of our design-approach, we realized a 3.57 mm(2) radix-4-based 8x parallel turbo-decoder ASIC in 0.13 mu m CMOS technology achieving 390 Mb/s. At the more realistic 100 Mb/s LTE milestone targeted by industry today, the turbo-decoder consumes only 69 mW.
引用
收藏
页码：8 / 17
页数：10
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