Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

被引：24

作者：

Berg, Martin ^{[1
,2
]}

Kilpi, Olli-Pekka ^{[1
]}

Persson, Karl-Magnus ^{[1
,3
]}

Svensson, Johannes ^{[1
]}

Hellenbrand, Markus ^{[1
]}

Lind, Erik ^{[1
]}

Wernersson, Lars-Erik ^{[1
]}

机构：

[1] Lund Univ, Dept Elect & Informat Technol, SE-22100 Lund, Sweden

[2] Lund Univ, Div Solid State Phys, SE-22100 Lund, Sweden

[3] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2016年 / 37卷 / 08期

基金：

欧盟地平线“2020”;

关键词：

Vertical; nanowire; InAs; MOSFET; transistor; gate-last; self-aligned; TRANSISTORS;

D O I：

10.1109/LED.2016.2581918

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON-and OFF-performance, exhibiting an ON-current of 0.14 mA/mu m, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/mu m. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.

引用

页码：966 / 969

页数：4

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