A configurable processor synthesis system

被引：16

作者：

Gay, Wanda ^{[1
]}

Gloster, Clay, Jr. ^{[1
]}

机构：

[1] Howard Univ, Dept Elect & Comp Engn, Washington, DC 20059 USA

来源：

FCCM 2007: 15TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2007年

关键词：

D O I：

10.1109/FCCM.2007.43

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we present a Configurable Digital Signal Processor Synthesis (CPS) System that produces a library of high-performance processors wherein each processor executes a specific digital signal processing (DSP) algorithm. Each processor contains a small instruction set and implements a particular application. These algorithm specific DSPs (ASDSPs) are used to alleviate bottlenecks in software by replacing computationally intense portions of a high level DSP algorithm with custom hardware. Each ASDSP generated by the CPS system is individually loaded into a commercially available configurable system. A library of algorithm specific DSPs for a sample application set of fundamental complex arithmetic modules is generated using the CPS system. The resulting library of floating point processors is implemented on a Firebird FPGA board containing a Virtex XCV2000E FPGA part. The results are compared with a comparable software algorithm implemented on a 2.79 GHz Pentium IV general purpose processor. This comparison shows that, despite having a clock speed that is an order of magnitude slower than the microprocessor (54MHZ versus 2.79 GHZ), the proposed ASDSP ran an order of magnitude (13X) faster than the microprocessor implementation in the best case.

引用

页码：331 / +

页数：2