Impact of Process-Induced Inclined Sidewalls on Gate-Induced Drain Leakage (GIDL) Current of Nanowire GAA MOSFETs

被引：9

作者：

Maniyar, Ashraf ^{[1
]}

Srinivas, P. S. T. N. ^{[1
]}

Tiwari, Pramod Kumar ^{[1
]}

Chang-Liao, Kuei-Shu ^{[2
]}

机构：

[1] Indian Inst Technol Patna, Dept Elect Engn, Patna 801106, Bihar, India

[2] Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu 30013, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2022年 / 69卷 / 09期

关键词：

Fabrication; gate induced drain leakage (GIDL); MOSFET; trapezoidal cross section; SCALING LENGTH MODEL; FINFET; PERFORMANCE; DESIGN;

D O I：

10.1109/TED.2022.3194109

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The shape of the channel cross section in rectangular nanowire (NW) gate-all-around (GAA) MOSFETs turns trapezoidal due to process variations. In this article, the impact of process-induced inclination of sidewalls on gate-induced drain leakage (GIDL) current in the trapezoidal channel NW GAA MOSFETs has been systematically investigated using experimental and calibrated TCAD simulation results. The GIDL current has also been analyzed against the variation in other device parameters, such as channel length, height, and width. The lateral band-to-band tunneling (L-BTBT) mechanism at the channel/drain junction has been considered in simulations to obtain the GIDL current. The investigation reveals that the GIDL current increases up to two times if the process-induced sidewalls inclination angle increases from 0 degrees to 20 degrees.

引用

页码：4815 / 4820

页数：6

共 28 条

[1] Bae G, 2018, INT EL DEVICES MEET
[2] Chan T. Y., 1987, 1987 International Electron Devices Meeting, IEDM. Technical Digeset (Cat. No.87CH2515-5), P718, DOI 10.1109/IEDM.1987.191531
[3] SUB-BREAKDOWN DRAIN LEAKAGE CURRENT IN MOSFET
CHEN, J
CHAN, TY
CHEN, IC
KO, PK
HU, C
[J]. IEEE ELECTRON DEVICE LETTERS, 1987, 8 (11) : 515 - 517
[4] Chen J., 1992, P IEEE INT SOI C PON, P84, DOI [10.1109/SOI.1992.664806, DOI 10.1109/SOI.1992.664806]
[5] Duarte JP, 2013, 2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013), P135
[6] A 3-D analytical physically based model for the subthreshold swing in undoped trigate FinFETs
El Hamid, Hamdy Abd
Guitart, Jaume Roig
Kilchytska, Valeria
Flandre, Denis
Iniguez, Benjamin
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (09) : 2487 - 2496
[7] Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors
Fan, Jiewen
Li, Ming
Xu, Xiaoyan
Yang, Yuancheng
Xuan, Haoran
Huang, Ru
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (01) : 213 - 219
[8] Compact Modeling of Nanoscale Trapezoidal FinFETs
Fasarakis, Nikolaos
Karatsori, Theano A.
Tsormpatzoglou, Andreas
Tassis, Dimitrios H.
Papathanasiou, Konstantinos
Bucher, Matthias
Ghibaudo, Gerard
Dimitriadis, Charalabos A.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (02) : 324 - 332
[9] A Quasi-3-D Scaling Length Model for Trapezoidal FinFET and Its Application to Subthreshold Behavior Analysis
Gao, Hong-Wun
Wang, Yeong-Her
Chiang, Te-Kuang
[J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (02) : 281 - 289
[10] Fin Shape Impact on FinFET Leakage With Application to Multithreshold and Ultralow-Leakage FinFET Design
Gaynor, Brad D.
Hassoun, Soha
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (08) : 2738 - 2744

← 1 2 3 →