A High Gain, High Power K-Band Frequency Doubler in 0.18 μm CMOS Process

被引：12

作者：

Chen, Jung-Hau ^{[1
,2
]}

Wang, Huei ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 106, Taiwan

[2] Natl Taiwan Univ, Grad Inst Commun Engn, Taipei 106, Taiwan

来源：

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2010年 / 20卷 / 09期

关键词：

CMOS; current-reuse; K-band frequency doubler; CIRCUIT; GHZ;

D O I：

10.1109/LMWC.2010.2057412

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A K-band frequency doubler with a current-reuse technique implemented using 0.18 mu m CMOS process is presented in this letter. This frequency doubler exhibits a high conversion gain of -0.5 similar to -4.5 dB from 18 to 26 GHz with 0 dBm input drive power, and good fundamental rejection of 30 to 50 dB. The dc power consumption is 18.2 to 20.8 mW, and the chip size is 0.54 x 0.53 mm(2). To the author's knowledge, this frequency doubler achieves the highest conversion gain and output power among all K-band CMOS frequency doublers to date.

引用

页码：522 / 524

页数：3

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