Equalization and clock and data recovery techniques for 10-gb/s CMOS serial-link receivers

被引：164

作者：

Gondi, Srikanth ^{[1
]}

Razavi, Behzad ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2007年 / 42卷 / 09期

关键词：

adaptive equalization; analog equalization; broadband receivers; DFE; FFE; high-speed links; lossy channel; reverse scaling;

D O I：

10.1109/JSSC.2007.903076

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-mu m CMOS technology. Using techniques such as reverse scaling, passive peaking networks, and dual- and triple-loop adaptation, the prototypes adapt to FR4 trace lengths up to 24 inches. The equalizer/CDR circuit retimes the data with a bit error rate of 10(-13) while consuming 133 mW from a 1.6-V supply.

引用

页码：1999 / 2011

页数：13

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