PulseDL: A reconfigurable deep learning array processor dedicated to pulse characterization for high energy physics detectors
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作者:
Ai, Pengcheng
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Cent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R ChinaCent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R China
Ai, Pengcheng
[1
]
Wang, Dong
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Cent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R ChinaCent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R China
Wang, Dong
[1
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Huang, Guangming
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Cent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R ChinaCent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R China
Huang, Guangming
[1
]
Shen, Fan
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Cent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R ChinaCent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R China
Shen, Fan
[1
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Fang, Ni
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Cent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R ChinaCent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R China
Fang, Ni
[1
]
Xu, Deli
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Cent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R ChinaCent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R China
Xu, Deli
[1
]
Wang, Hui
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Cent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R ChinaCent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R China
Wang, Hui
[1
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Chen, Junling
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Cent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R ChinaCent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R China
Chen, Junling
[1
]
机构:
[1] Cent China Normal Univ, 152 Luoyu Rd, Wuhan 430079, Hubei, Peoples R China
Neural network models show promising speed and accuracy for online and on-site data analysis in high energy physics. In this report, we discuss a multi-functional neural computing chip called PulseDL for measurement of pulse characteristics. We adopted a structure with outside RISC CPU and processing engines in PulseDL for balanced power and performance. Digital logic at register transfer level was specially designed with emphasis on thread level parallelism. Based on the hardware scheme, we co-designed the network architecture to best utilize the on-chip resources. Convolution, deconvolution and fully-connected matrix multiplication of the network were fitted into the hardware with reconfiguration during runtime. The chip has been taped out under the GSMCR013 130 nm process, with 4.9 mm x 4.9 mm area, at least 25 MHz working frequency and 1.2 V core voltage. Measured by post-layout simulations, the peak power efficiency of the chip was estimated to be about 12 giga operations per second per watt.