A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology

被引：4

作者：

Chung, Ching-Che ^{[1
]}

Lo, Chi-Kuang ^{[1
]}

机构：

[1] Natl Chung Cheng Univ, Dept Comp Sci & Informat Engn, 168 Univ Rd, Chiayi 621, Taiwan

来源：

IEICE ELECTRONICS EXPRESS | 2016年 / 13卷 / 17期

关键词：

all-digital phase-locked loop; fast lock-in; low power; FREQUENCY-SYNTHESIZER; ADPLL; PLL; FILTER;

D O I：

10.1587/elex.13.20160749

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A system-on-a-chip (SoC) requires several phase-locked loops (PLLs) for providing different clock frequencies to different modules. Usually, analog PLLs cannot be stopped due to their long setting time. Hence, these PLLs dominate the system's standby power consumption. In this paper, a fast lock-in all-digital PLL (ADPLL) that can achieve lock-in within 4.5 clock cycles is proposed to ensure that it can be switched off in the low power mode. The output frequency of the proposed ADPLL ranges from 125 MHz to 1.47 GHz, and the power consumption is 0.98 mW (at 0.9 V, 1.47 GHz).

引用

页数：10

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