A wide-bandwidth 2.4 GHz ISM band fractional-N PLL with adaptive phase noise cancellation

被引:82
作者
Swaminathan, Ashok [1 ]
Wang, Kevin J. [1 ]
Galton, Ian [1 ]
机构
[1] Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92093 USA
关键词
calibration; CMOS analog integrated circuits; phase-locked loops (PLLs);
D O I
10.1109/JSSC.2007.908763
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A fast-settling adaptive calibration technique is presented that makes phase noise cancelling Delta E fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz; ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip loop filter. In addition to the adaptive calibration technique, the IC incorporates a dynamic charge pump biasing technique to reduce power dissipation. The worst-case phase noise of the IC is -101 dBc/Hz and -124 dBc/Hz at 100 kHz and 3 MHz offsets, respectively, and the adaptive phase noise cancellation technique has a worst-case settling time of 35 mu s. The IC is implemented in 0.18 mu m CMOS technology. It measures 2.2 x 2.2 mm(2), and its core circuitry consumes 20.9 mA from a 1.8 V supply.
引用
收藏
页码:2639 / 2650
页数:12
相关论文
共 17 条
[1]  
CHAN KL, 2006, IEEE ISSCC DIG TECH, P390
[2]   A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration [J].
Gupta, Manoj ;
Song, Bang-Sup .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) :2842-2851
[3]  
Lee RA, 2001, VIVARIUM, V39, P1
[4]   A quad-band GSM-GPRS transmitter with digital auto-calibration [J].
Lee, ST ;
Fang, SJ ;
Allstot, DJ ;
Bellaouar, A ;
Fridi, AR ;
Fontaine, PA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (12) :2200-2214
[5]   A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise [J].
Meninger, SE ;
Perrott, MH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (04) :966-980
[6]  
MILLER B, 1990, PROCEEDINGS OF THE 44TH ANNUAL SYMPOSIUM ON FREQUENCY CONTROL 1990, P559, DOI 10.1109/FREQ.1990.177545
[7]   A MULTIPLE MODULATOR FRACTIONAL DIVIDER [J].
MILLER, B ;
CONLEY, RJ .
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 1991, 40 (03) :578-583
[8]   A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-MB/s in-loop modulation [J].
Pamarti, S ;
Jansson, L ;
Galton, I .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (01) :49-62
[9]   Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs [J].
Pamarti, S ;
Galton, I .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2003, 50 (11) :829-838
[10]   Statistics of the quantization noise in 1-bit dithered single-quantizer digital delta-sigma modulators [J].
Pamarti, Sudhakar ;
Welz, Jared ;
Galton, Ian .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (03) :492-503