Field Programmable Gate Arrays and Application Specific Integrated Circuits Implementation of COordinate Rotation Digital Computer Using Wave-Pipelined Circuits

Higher operating frequencies can be achieved in Wave-Pipelined (WP) circuits, by adjusting the clock periods and clock skews so as to latch the outputs of combinational logic circuits at the stable periods. Major contributions of this paper are the proposal for the use of soft-core processor for the automation of the above tasks, and the superiority of the WP circuits with regard to power dissipation. The proposed scheme is evaluated by COordinate Rotation Digital Computer (CORDIC) algorithm using three different schemes: wave-pipelining, pipelining and non-pipelining. The System-On-Chip (SOC) approach is adopted for implementation on Altera Field Programmable Gate Arrays (FPGAs) based SOPC kits with Nios II soft-core processor. The above scheme is also implemented and tested by using ASIC. From the implementation results, it is verified that the WP circuits are faster compared to non-pipelined circuits. The pipelined circuits are found to be faster than the WP circuits and this is achieved at the cost of increase in area and power.