6.6+GHz low Vmin, read and half select disturb-free 1.2 mb SRAM

被引：41

作者：

Joshi, R. ^{[1
]}

Houle, R. ^{[1
]}

Batson, K. ^{[1
]}

Rodko, D. ^{[1
]}

Patel, P. ^{[1
]}

Huott, W. ^{[1
]}

Franch, R. ^{[1
]}

Chan, Y. ^{[1
]}

Plass, D. ^{[1
]}

Wilson, S. ^{[1
]}

Wang, P. ^{[1
]}

机构：

[1] IBM Res, Yorktown Hts, NY USA

来源：

2007 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIC.2007.4342738

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully functional read and half select disturb-free 1.2 Mb SRAM is demonstrated. Measured results show an operating g range of 0.4 V to 1.5 V and -25 degrees C to 100 degrees C speed of 6.6+ GHz at IV 25 degrees C and yield of 90-100%.

引用

页码：250 / 251

页数：2

共 5 条

[1]

Chang L, 2005, 2005 Symposium on VLSI Technology, Digest of Technical Papers, P128

[2]

HENKELS W, 2001, Patent No. 6279144

[3]

JOSHI R, 2004, ESSCIRC P, P411

[4]

Leobandung E, 2005, 2005 Symposium on VLSI Technology, Digest of Technical Papers, P126

[5] Timing uncertainty measurements an the Power5 microprocessor [J].

Restle, PJ ;

Franch, RL ;

James, NK ;

Huott, WV ;

Skergan, TM ;

Wilson, SC ;

Schwartz, NS ;

Clabes, JG .

2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 :354-355

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