A monolithic voltage-boosting parallel-primary transformer structures for fully integrated CMOS power amplifier design

In this paper, a novel monolithic voltage-boosting parallel-primary transformer is presented for the fully integrated CMOS power amplifier design. Multiple primary loops are interweaved in parallel to combine the AC currents from multiple power devices while the higher turn ratio of a secondary loop boosts AC voltages of the combined primary loops at the load of the secondary loop. The proposed interweaved structure is much more compact and separable from power devices, avoiding potential instability. To verify the feasibility of this power combining method, the fully integrated CMOS switching power amplifier was implemented in a standard 0.18-mu m technology. The power amplifier successfully demonstrated a measured output power of 1.3 W and a measured power added efficiency (PAE) of 41% to a 50-92 load with a 3.3-V power supply at 1.8 GHz operation.