Operating system integration and performance of a multi stream cipher architecture for reconfigurable system-on-chip

被引：0
作者：
Wee, C. M. [1 ]
Sutton, P. R. [1 ]
Bergmann, N. W. [1 ]
机构：
[1] Univ Queensland, Sch Informat Technol & Elect Engn, Brisbane, Qld 4072, Australia
来源：
FCCM 2007: 15TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2007年
关键词：
D O I：
10.1109/FCCM.2007.19
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes the integration and performance of a multi-stream cipher core with a uClinux Microblaze based reconfigurable System-on-Chip that uses the. Open Crypto Framework. This allows applications to access the multi stream cipher core via kernel space calls.
引用
收藏
页码：283 / +
页数：2
相关论文
共 50 条
  • [31] A fast and accurate validation technique for operating system in multi-processor system-on-chip design
    Bacivarov, I
    Jerraya, AA
    Yoo, S
    ADVANCED TOPICS IN OPTOELECTRONICS, MICROELECTRONICS, AND NANOTECHNOLOGIES, 2002, 5227 : 342 - 348
  • [32] A HIGH PERFORMANCE SYSTEM-ON-CHIP ARCHITECTURE FOR DIGITAL WIDEBAND RADAR RECEIVER
    Pang, Long
    Zhao, Min
    Luo, Yue-dong
    2014 12TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING (ICSP), 2014, : 2106 - 2109
  • [33] Low power system-on-chip platform architecture for high performance applications
    Lo, WC
    Erdogan, A
    Arslan, T
    SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, 2003, : 349 - 356
  • [34] Programmable parallel coprocessor architectures for reconfigurable system-on-chip
    Williams, J
    Bergmann, N
    2004 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS, 2004, : 193 - 200
  • [35] A dynamically reconfigurable system-on-chip for implementing wireless MACs
    Nabi, Syed Waqar
    Wells, Cade C.
    Vanderbauwhede, Wim
    2007 PH.D RESEARCH IN MICROELECTRONICS AND ELECTRONICS, 2007, : 37 - +
  • [36] Prototyping of a 5 GHz WLAN reconfigurable System-on-Chip
    Blionas, S
    Masselos, K
    Dre, C
    Drosos, C
    Ieromnimon, F
    Metafas, D
    Pagonis, T
    Pnevmatikakis, A
    Tatsaki, A
    Trimis, T
    Vontzalidis, A
    Vontzalidist, A
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2003, E86D (05) : 891 - 900
  • [37] An embedded DRAM macro architecture for system-on-chip
    Sunaga, T
    Hosokawa, K
    Watanabe, S
    Mori, M
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, 2001, 26 (3-4): : 131 - 134
  • [38] An efficient bus architecture for system-on-chip design
    Cordan, B
    PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1999, : 623 - 626
  • [39] Non-Rectangular Reconfigurable Cores for System-on-Chip
    Alves, Pedro
    Ferreira, Joao Canas
    VLSI CIRCUITS AND SYSTEMS IV, 2009, 7363
  • [40] RtrASSoc - An adaptable superscalar reconfigurable system-on-chip the simulator
    Silva, JL
    Costa, RM
    Jorge, GHR
    3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2003, : 196 - 200
12345