High Performance Pipelined FPGA Implementation of the SHA-3 Hash Algorithm

被引：0

作者：

Ioannou, Lenos ^{[1
]}

Michail, Harris E. ^{[1
]}

Voyiatzis, Artemios G. ^{[2
]}

机构：

[1] Cyprus Univ Technol, Dept Elect Engn Comp Engn & Informat, CY-3036 Lemesos, Cyprus

[2] SBA Res, Vienna, Austria

来源：

2015 4TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO) | 2015年

关键词：

SHA-3; hash algorithm; FPGA; pipeline; high performance;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The SHA-3 cryptographic hash algorithm is standardized in FIPS 202. We present a pipelined hardware architecture supporting all the four SHA-3 modes of operation and a high-performance implementation for FPGA devices that can support both multi-block and multi-message processing. Experimental results on different FPGA devices validate that the proposed design achieves significant throughput improvements compared to the available literature.

引用

页码：68 / 71

页数：4

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