A Sparse Matrix Vector Multiply Accelerator for Support Vector Machine

被引：0

作者：

Nurvitadhi, Eriko ^{[1
]}

Mishra, Asit ^{[1
]}

Marr, Debbie ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

2015 INTERNATIONAL CONFERENCE ON COMPILERS, ARCHITECTURE AND SYNTHESIS FOR EMBEDDED SYSTEMS (CASES) | 2015年

关键词：

Hardware accelerator; machine learning; support vector machine; Algorithms; Performance; Design;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Sparse matrix vector multiplication (SpMV) is a linear algebra construct commonly found in machine learning (ML) algorithms, such as support vector machine (SVM). We profiled a popular SVM software (libSVM) on an energy-efficient microserver and a high-performance server for real-world ML datasets, and observed that SpMV dominates runtime. We propose a novel SpMV algorithm tailored for ML and a hardware accelerator architecture design based on this algorithm. Our evaluations show that the proposed algorithm and hardware accelerator achieves significant efficiency improvements over the conventional SpMV algorithm used in libSVM.

引用

页码：109 / 116

页数：8