Analyzing the Nonlinearity of Binary Phase Detector in Phase-Locked Loops

被引：0

作者：

Ni, Liya Grace ^{[1
]}

Xu, Xuelin ^{[2
]}

机构：

[1] Calif Baptist Univ, Dept Elect & Comp Engn, 8432 Magnolia Ave, Riverside, CA 92504 USA

[2] Luxtera Inc, Kanazawa, Ishikawa 92011, Japan

来源：

2014 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT): SILICON TECHNOLOGY HEATS UP FOR THZ | 2014年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Clock Data Recovery (CDR) circuits based on binary phase detector gained popularity in the last decade. In this paper, nonlinear control theory, specifically describing function, is employed to analyze the stability of PLL circuits for both ideal binary phase detector (BPD) and BPD with consideration of metastability. The significance of loop delay and metastability are discussed. The derived results can be used to guide the loop design.

引用

页数：3

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