This paper describes a programming environment for a broad range of digital target architectures ranging from standard microprocessors and microcontrollers to fine and coarse grained M1MD systems, programmable logic, and heterogeneous systems built from the former. Basically an interactive compiler, the environment offers simple input syntaxes to describe an application as a network of processes and the algorithms used therein to the level of their dataflow. To this, an explicit hardware model of the heterogeneous target is added distinguishing classes of processing elements of similar computational capabilities and the syntax to specify their usage in the application processes. Only two types of statements are needed for the hardware description and the SW to HW mapping. In view of the diversify of target architectures code generation in conventional compilers has to be substituted by a more general notion of resource allocation. The environment allows to plug in allocator modules for the different processor classes that encapsulate such diverse topics as task allocation, netlist generation and instruction scheduling. The environment is in use for several real targets. We outline an implementation on a non-standard, fine-grained configurable MIMD network of DSPs.
