Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

被引：0

作者：

Bangsaruntip, S. ^{[1
]}

Balakrishnan, K. ^{[1
]}

Cheng, S. -L. ^{[1
]}

Chang, J. ^{[1
]}

Brink, M. ^{[1
]}

Lauer, I. ^{[1
]}

Bruce, R. L. ^{[1
]}

Engelmann, S. U. ^{[1
]}

Pyzyna, A. ^{[1
]}

Cohen, G. M. ^{[1
]}

Gignac, L. M. ^{[1
]}

Breslin, C. M. ^{[1
]}

Newbury, J. S. ^{[1
]}

Klaus, D. P. ^{[1
]}

Majumdar, A. ^{[1
]}

Sleight, J. W. ^{[1
]}

Guillorn, M. A. ^{[1
]}

机构：

[1] IBM Res Div TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.

引用

页数：4

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