Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

被引：0

作者：

Bangsaruntip, S. ^{[1
]}

Balakrishnan, K. ^{[1
]}

Cheng, S. -L. ^{[1
]}

Chang, J. ^{[1
]}

Brink, M. ^{[1
]}

Lauer, I. ^{[1
]}

Bruce, R. L. ^{[1
]}

Engelmann, S. U. ^{[1
]}

Pyzyna, A. ^{[1
]}

Cohen, G. M. ^{[1
]}

Gignac, L. M. ^{[1
]}

Breslin, C. M. ^{[1
]}

Newbury, J. S. ^{[1
]}

Klaus, D. P. ^{[1
]}

Majumdar, A. ^{[1
]}

Sleight, J. W. ^{[1
]}

Guillorn, M. A. ^{[1
]}

机构：

[1] IBM Res Div TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.

引用

页数：4

共 50 条

[21] Design and optimization considerations for bulk gate-all-around nanowire MOSFETs
Song, Yi
Xu, Qiuxia
Zhou, Huajie
Cai, Xiaowu
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2009, 24 (10)
[22] Performance and Variability Studies of InGaAs Gate-all-Around Nanowire MOSFETs
Conrad, Nathan
Shin, SangHong
Gu, Jiangjiang
Si, Mengwei
Wu, Heng
Masuduzzaman, Muhammad
Alam, Mohammad A.
Ye, Peide D.
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2013, 13 (04) : 489 - 496
[23] Characterization of Interface Trap Density of In-rich InGaAs Gate-all-around Nanowire MOSFETs
Rahman, Fahim Ur
Hossain, Md. Shafayat
Khan, Saeed Uz Zaman
Zaman, Rifat
Hossen, Md. Obaidul
Khosru, Quazi D. M.
2012 7TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (ICECE), 2012,
[24] Statistical Device Simulation of Characteristic Fluctuation of 10-nm Gate-All-Around Silicon Nanowire MOSFETs Induced by Various Discrete Random Dopants
Sung, Wen-Li
Chang, Han-Tung
Chen, Chieh-Yang
Chao, Pei-Jung
Li, Yiming
2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2016, : 951 - 954
[25] Design study of the gate-all-around silicon nanosheet MOSFETs
Lee, Yongwoo
Park, Geon-Hwi
Choi, Bongsik
Yoon, Jinsu
Kim, Hyo-Jin
Kim, Dae Hwan
Kim, Dong Myong
Kang, Min-Ho
Choi, Sung-Jin
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 35 (03)
[26] 3-D Modeling of Fringing Gate Capacitance in Gate-all-around Cylindrical Silicon Nanowire MOSFETs
An, TaeYoon
Kim, SoYoung
2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013), 2013, : 256 - 259
[27] Fully gate-all-around silicon nanowire CMOS devices
Institute of Microelectronics, Singapore, Singapore
Solid State Technol, 2008, 5 (34-37):
[28] Fully gate-all-around silicon nanowire CMOS devices
Singh, N.
Buddharaju, K. D.
Agarwal, A.
Rustagi, S. C.
Lo, G. Q.
Balasubramanian, N.
Kwong, D. L.
SOLID STATE TECHNOLOGY, 2008, 51 (05) : 34 - 37
[29] Gate-all-around twin silicon nanowire SONOS memory
Suk, Sung Dae
Yeo, Kyoung Hwan
Cho, Keun Hwi
Li, Ming
Yeoh, Yun young
Hong, Ki-Ha
Kim, Sung-Han
Koh, Young-Ho
Jung, Sunggon
Jang, WonJun
Kim, Dong-Won
Park, Donggun
Ryu, Byung-Il
2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 142 - +
[30] Gate-All-Around Silicon Nanowire Devices: Are these the Future of CMOS?
Lo, G. Q.
Singh, N.
Rustagi, S. C.
Buddharaju, K. D.
Balasubramanian, N.
Kwong, D. L.
SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES, 2008, 16 (10): : 729 - 729

← 1 2 3 4 5 →