On-line integrity monitoring of microprocessor control logic

被引：3

作者：

Kim, S ^{[1
]}

Somani, AK ^{[1
]}

机构：

[1] Iowa State Univ Sci & Technol, Dept Elect & Comp Engn, Ames, IA 50011 USA

来源：

MICROELECTRONICS JOURNAL | 2001年 / 32卷 / 12期

关键词：

fault tolerant microprocessor; soft error; concurrent integrity checking; fault injection simulation; fault sensitivity;

D O I：

10.1016/S0026-2692(01)00090-8

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a low-cost reliability enhancement strategy for the microprocessor's control logic, which usually remains unprotected against soft errors due to great overhead. We classify control signals into static and dynamic control depending on their changeability. For static control, signals used in pipeline stages are integrated into a signature and verified with a cached check code at commit time. The concept of caching signatures is introduced. Dynamic control is examined on the spot in which the signals are created using component-level duplication. Fault injection simulations on a SimR2K processor demonstrate that our schemes can achieve more than 99% coverage on average with a very small hardware addition. (C) 2001 Elsevier Science Ltd. AB rights reserved.

引用

页码：999 / 1007

页数：9

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