Stacking fault formation in highly doped 4H-SiC epilayers during annealing

Spontaneous stacking fault formation during annealing in n(+) 4H-SiC epilayers deposited on the n(-) 4H-SiC substrates has been analyzed by conventional and high-resolution transmission electron microscopy (HRTEM). All faults were double layer Shockley faults formed by glide of partial dislocations on two neighboring basal planes. Ends of stacking faults were examined with high-resolution TEM. Approximately half of bounding partial dislocations had extra half planes extending into the substrate while the other half had half planes pointing toward epilayer. This observation is inconsistent with mechanical stress due to doping difference between epilayer and the substrate being the driving force of fault expansion. Formation of single Shockley stacking faults was also observed in n(+) 6H-SiC.