Prevention of plasma induced damage on thin gate oxide of HDP oxide deposition, metal etch, Ar preclean processing in BEOL sub-half micron CMOS processing.

In this paper a comparison is made of several PID measurement techniques. A novel mechanism of plasma induced damage (PID) by high density plasma (HDP) inter metal dielectric (IMD) deposition is proposed. Results of a design of experiment (DOE) on Ar preclean minimizing PID are presented. For metal etch, HDP etch is compared reactive ion etch and the impact of individual process steps are identified by specialized antenna structures. Measurement results of Charge Pumping (CP) breakdown voltage (V-bd) and gate oxide leakage are correlating very well. For HDP oxide deposition, plasma damage is minimal, assuring minimal exposure time of the metal line to the plasma using maximal deposition to sputter ratio. This process is inducing less PID than the classic SOG processing. Ar preclean induces minimal plasma damage using minimal process time, high ion energy and high plasma power. On metal etch, reactive ion etch is inducing less plasma damage then HDP etching. For both reactors PID is induced only in the metal over etch step.