Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence

被引:0
作者
Saha, Prasenjit [1 ]
Kalluru, Hema Sai [1 ]
Abbas, Zia [1 ]
机构
[1] Int Inst Informat Technol Hyderabad IIIT H, Ctr VLSI & Embedded Syst Technol CVEST, Hyderabad 500032, India
来源
2021 34TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2021 20TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID & ES 2021) | 2021年
关键词
Spider Monkey Optimization; Leakage Power; Propagation delays; PVT Variations; Transistor Sizing; CMOS; VLSI;
D O I
10.1109/VLSID51830.2021.00045
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper deals with transistor sizing based static power optimization for multi-stage CMOS circuits using swarm intelligence algorithm. The overall circuit performance is improved by optimizing the individual basic cell performances. Optimized cells are re-used at places with similar circuit scenarios thereby reducing the number of variables to work with. At each stage of execution, the algorithm generates multiple sizing options for basic cells with varying power-delay specifications to choose from. This work proposes a dual sizing approach for critical and non-critical path cells. The overall process has low circuit dependence and has been applied on a wide range of single and multi-stage circuits (including ISCAS benchmark circuits). The approach considers fabrication process parameter variations (for +/- 3 sigma design) in addition to a wide range of temperature (-55 degrees C to 125 degrees C) and supply voltage (+/- 10%) variations for robust sizing solutions. Results show leakage reductions up to 63.6%.
引用
收藏
页码:234 / 239
页数:6
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