Investigation of Hot-Carrier Degradation in 0.18-μm MOSFETs for the Evaluation of Device Lifetime and Digital Circuit Performance

In this work, we investigate the hot-carrier reliability in 0.18 mu m MOSFET technology that is being extensively employed in various analog/digital applications. Hot-carrier degradation in MOSFETs is known to follow power-law relation where the time exponent of the degradation curve can be utilized to quantify the device ageing. Here, we examine the dependency of time power-law exponent on different gate stress bias to determine the physical mechanism responsible for device degradation. Extensive consideration is given to the maximum impact ionization condition Vgs=Vds/2 and maximum hot-electron injection condition Vgs=Vds. Time evolution of degradation curve depicts changing slope with increasing stress duration. This variation in time power-law exponent over different stress time intervals is an important indicator of changing degradation mechanism as the device ages. Since the operating conditions for a device directly relates to its targeted application, therefore DC lifetime prediction under the influence of different Vgs/Vds stress bias combinations is performed to determine the limiting case challenging the circuit integrity. Also, the impact of hot-carrier degradation on the circuit delay under the aforementioned stress conditions is evaluated for typical digital CMOS circuits. Effective switching current methodology is employed for the delay analysis in transistor stacks that comprise inverter, NAND, and NOR circuits to show the adverse effects of the damage caused by the hot-carriers.