A 1.0-GHz single-issue 64-bit PowerPC integer processor

被引:23
作者
Silberman, J [1 ]
Aoki, N
Boerstler, D
Burns, JL
Dhong, S
Essbaum, A
Ghoshal, U
Heidel, D
Hofstee, P
Lee, KT
Meltzer, D
Ngo, H
Nowka, K
Posluszny, S
Takahashi, O
Vo, I
Zoric, B
机构
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Heights, NY 10589 USA
[2] IBM Corp, Austin Res Lab, Austin, TX 78758 USA
[3] IBM Corp, Microelect, Austin, TX 78758 USA
关键词
computer architecture; CMOS integrated circuits; high-speed integrated circuits; integrated circuit design; logic design; microprocessors;
D O I
10.1109/4.726542
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The organization and circuit design of a 1.0-GHz integer processor built in 0.25-mu m CMOS technology are presented, A microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented.
引用
收藏
页码:1600 / 1608
页数:9
相关论文
共 14 条
[1]  
BOERSTLER D, IN PRESS 1998 S VLSI
[2]  
BURNS J, IN PRESS 1998 S VLSI
[3]   A 2-NS CYCLE, 3.8-NS ACCESS 512-KB CMOS ECL SRAM WITH A FULLY PIPELINED ARCHITECTURE [J].
CHAPPELL, TI ;
CHAPPELL, BA ;
SCHUSTER, SE ;
ALLAN, JW ;
KLEPNER, SP ;
JOSHI, RV ;
FRANCH, RL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (11) :1577-1585
[4]  
GIESEKE B, 1997, ISSCC FEB, P176
[5]   Self resetting logic register and incrementer [J].
Haring, RA ;
Milshtein, MS ;
Chappell, TI ;
Dhong, SH ;
Chappell, BA .
1996 SYMPOSIUM ON VLSI CIRCUITS - DIGEST OF TECHNICAL PAPERS, 1996, :18-19
[6]  
HEALD R, 1998, ISSCC, P350
[7]  
HEIDEL D, 1998, IN PRESS P VLSI TEST
[8]   PARALLEL ALGORITHM FOR EFFICIENT SOLUTION OF A GENERAL CLASS OF RECURRENCE EQUATIONS [J].
KOGGE, PM ;
STONE, HS .
IEEE TRANSACTIONS ON COMPUTERS, 1973, C-22 (08) :786-793
[9]  
LEE YH, 1997, IEICE T INFORM SYS D, V380, P98
[10]  
ROHRER N, 1998, ISSCC, P240