Characterization and estimation of circuit reliability degradation under NBTI using on-line IDDQ measurement

Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characterize and estimate the lifetime circuit reliability under NBTI degradation. Unlike conventional approaches, where a representative f(MAX) (maximum operating frequency) measurement from timing critical circuitry is used, we propose to utilize the standby circuit leakage I-DDQ as a metric to detect and characterize temporal NBTI degradation in digital circuits. Compared to the f(MAX) based approach, the proposed IDDQ based technique benefits from lower test cost and improved capability of estimating reliability of complex circuitries such as ALUs and SRAM arrays. We have derived an analytical expression for circuit I-DDQ from the analytical PMOS V-t degradation model (Delta V-t alpha t(1/6)). The proposed model is verified with measurement data obtained from a test chip fabricated in 130nm technology. Furthermore, we examine the possible applications of our proposed I-DDQ based NBTI characterization. We show that the temporal degradation in static noise margin (SNM) of SRAM array and f(MAX) of random logic circuits are highly correlated to the I-DDQ measurement, and this relationship can be used to predict long term circuit reliability.