Design and Signal Integrity Analysis of High Bandwidth Memory (HBM) Interposer in 2.5D Terabyte/s Bandwidth Graphics Module

被引：0

作者：

Lee, Hyunsuk ^{[1
]}

Cho, Kyungjun ^{[1
]}

Kim, Heegon ^{[1
]}

Choi, Sumin ^{[1
]}

Lim, Jaemin ^{[1
]}

Shim, Hyunwoo ^{[1
]}

Kim, Joungho ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Daejeon, South Korea

来源：

2015 IEEE 24TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS | 2015年

关键词：

2.5D terabyte/s bandwidth graphics module; high bandwidth memory (HBM); HBM interposer; HBM interposer channel; signal integrity; insertion loss; far-end crosstalk (FEXT); eye-diagram;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM interposer has also been to the force. However, several signal integrity issues of the HBM interposer occur due to the manufacturing process constraints. In this paper, we design the HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM interposer, electrical performance of the HBM interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM interposer shows good signal integrity.

引用

页码：145 / 147

页数：3

共 4 条

[1]

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IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (06) :556-564

[3]

Standard J. E. D. E. C., 2013, JESD235 JEDEC

[4]

Zhang K., 2013, ISSCC 2013 TRENDS

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