Fabrication process of superconducting integrated circuits with submicron Nb/AlOx/Nb junctions using electron beam direct writing technique

被引:2
作者
Aoyagi, M
Nakagawa, H
机构
来源
EMERGING LITHOGRAPHIC TECHNOLOGIES | 1997年 / 3048卷
关键词
superconductivity; Nb; Josephson junction; integrated circuit; electron beam lithography; portable conformable mask (PCM) method; PMMA; CMS; ECR plasma etching;
D O I
10.1117/12.275805
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, me have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/alpha M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 mu m to 0.5 mu m at 0.1 mu m intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum I-c spread of +/- 13 % for 0.81-mu m-square (+/- 16 % for 0.67-mu m-square) 100 junctions spreading in 130-mu m-square area. The size deviation of 0.05 mu m was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-mu m-square junctions having a 50 4JL OR-gate chain, where 4JL means Four junctions Logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR-gate logic delay, where the minimum delay was 8.6 ps/gate.
引用
收藏
页码:396 / 403
页数:8
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