An Improved Seven-Level PUC Inverter Topology With Voltage Boosting

被引：75

作者：

Sathik, M. Jagabar ^{[1
]}

Bhatnagar, Kaustubh ^{[1
]}

Sandeep, N. ^{[2
]}

Blaabjerg, Frede ^{[3
]}

机构：

[1] SRM Inst Sci & Technol, Dept Elect & Elect, Chennai 603203, Tamil Nadu, India

[2] Natl Inst Technol Karnataka, Dept Elect & Elect, Surathkal 575025, India

[3] Aalborg Univ, Dept Energy Technol, DK-9220 Aalborg, Denmark

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2020年 / 67卷 / 01期

关键词：

Capacitors; Inverters; Voltage control; Topology; Switches; Modulation; Voltage measurement; Logic form equations; multilevel inverters; voltage balancing; voltage boosting; MULTILEVEL CONVERTER;

D O I：

10.1109/TCSII.2019.2902908

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief, a seven-level (7L) improved packed U-cell (IPUC) inverter with reduced power electronic components is proposed. The presented IPUC inverter has low voltage stress on switches and is capable of voltage boosting. A new voltage balancing method based on logic form equations is developed for regulating the inherent floating capacitor voltage to half the input dc voltage. The proposed 7L IPUC is compared with other state-of-the-art 7L inverters in terms of number of IGBTs, blocking voltage, and driver circuits for attesting its superior merits. The performance of the proposed voltage balancing is verified through a laboratory prototyped 7L IPUC inverter considering varying load conditions and the corresponding results are elucidated.

引用

页码：127 / 131

页数：5

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