Efficient Design and Implementation of Channelized Reconnaissance Receiver

被引:0
|
作者
Zhou, Xinxing [1 ]
Cai, Quanwang [1 ]
Wang, Zheng [1 ]
Wen, Fei [1 ]
Qiu, Yaoming [1 ]
机构
[1] CSIC, 722 Res Inst, Wuhan 430205, Hubei, Peoples R China
关键词
wideband channelized receiver; polyphase filter bank; FPGA; oversampling factor;
D O I
10.1145/3290420.3290478
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The traditional wideband digital channelized receiver in electronic warfare has problems of large amount of data, occupying too much computing resources and complex realization. In order to solve these problems, an optimization design method for channelization based on high processing rate is proposed. Firstly the mathematical model of channelization with arbitrary oversampling factor is derived theoretically, and the appropriate oversampling factor is chosen to establish the polyphase architecture. Secondly the polyphase filter bank is optimized to run at higher rate and all the operations of the channelization are designed to work at the same rate. The proposed method is successfully implemented on the hardware, and the result shows that the method is correct and easy to implement. Additionally its processing speed is fast and the computing resources are saved as well.
引用
收藏
页码:294 / 298
页数:5
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