System-in-package integration of passives using 3D through-silicon vias

Future generations of cellular RF transceivers require higher degrees of integration, preferably using the third dimension. System-in-Package (SiP) applications have been shown for integrated 3D "trench" capacitors in silicon with a new world record capacitance density of >= 400F/mm(2) and break-down voltage >6V using Atomic Layer Deposition (ALD) of multiple MIM layer stacks of high-k dielectrics (Al2O3) and conductive layers (TiN). Different techniques may be used for through-silicon via (TSV) drilling and filling to allow for 3D die and wafer stacking with a small form factor. Both dry and we methods were applied successfully in both the drilling and fill electrochemical etching yields ultrafine high aspect ratio (similar to 1.5 mu mx200 mu m) vias. A new "bottom-up" Cu-electroplating method and some preliminary Cu-paste filling tests show options for via metal formation.