Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility

被引：0

作者：

Zimpeck, Alexandra L. ^{[1
,2
]}

Meinhardt, Cristina ^{[3
]}

Artola, Laurent ^{[2
]}

Hubert, Guillaume ^{[2
]}

Kastensmidt, Fernanda L. ^{[1
]}

Reis, Ricardo ^{[1
]}

机构：

[1] Univ Fed Rio Grande Sul UFRGS, Inst Informat, PPGC PGMicro, Porto Alegre, RS, Brazil

[2] Univ Toulouse, ONERA DPHY, Toulouse, France

[3] Univ Fed Santa Catarina UFSC, Dept Informat & Estat, Florianopolis, SC, Brazil

来源：

2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2019年

关键词：

FinFET; reliability; soft error; process variability; mitigation; microelectronics; ASAP7;

D O I：

10.1109/icecs46596.2019.8965045

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper evaluates the potential of using the sleep transistor in FinFET logic cells to mitigate the process variability effects and the soft error susceptibility. The insertion of a sleep transistor improves up to 40.6% the delay variability and up to 12.4% the power variability. Moreover, the design with a sleep transistor became all logic cells investigated free of faults, independently of the supply voltage applied in the design.

引用

页码：582 / 585

页数：4

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