Quantum-size effects in sub 10-nm fin width InGaAs FinFETs

被引：0

作者：

Vardi, A. ^{[1
]}

Zhao, X. ^{[1
]}

del Alamo, J. A. ^{[1
]}

机构：

[1] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA

来源：

2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

InGaAs FinFETs with sub-10 nm fin widths were fabricated for the first time using precision dry etching and digital etch. We find that the threshold voltage, V-T, becomes highly sensitive to the fin width, W-f, in the sub-10 nm W-f range. 2D Poisson-Schrodinger simulations suggest that this is due to quantization effects. We also show that in the quantum regime, a sidewall slope below 85 degrees significantly reduce V-T variation at the same drawn dimensions.

引用

页数：4

共 6 条

[1] Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III-V Semiconductor) on Variation for Logic and SRAM Applications [J].