Concurrent logic and interconnect delay estimation of MOS circuits by mixed, algebraic and Boolean symbolic analysis

Accurate estimation of delay in logic-stages and interconnects is of utmost importance in digital VLSI design. Conventional delay estimation techniques are numeric in terms of design parameters for both logic-stages and interconnect trees driven by them. In this paper, we present a symbolic method of computing delay in logic stages followed by interconnect trees. For each stage, our method provides a single analytic delay expression that is symbolic in terms of all input logic assignments as well as transistor and interconnect parameters. The method has been implemented and validated on modern digital VLSI technologies.