A low-power integrated circuit for remote speech recognition

被引：1
作者：
Borgatti, M [1 ]
Felici, M [1 ]
Ferrari, A [1 ]
Guerrieri, R [1 ]
机构：
[1] Univ Bologna, DEIS, I-40136 Bologna, Italy
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 07期
关键词：
CMOS digital integrated circuits; digital signal processors; low-power circuits; low-voltage circuits; speech analysis; speech recognition;
D O I：
10.1109/4.701266
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a low-power, low-voltage speech processing system is presented. The system is intended to be used in remote speech recognition applications where feature extraction is performed on terminal and high-complexity recognition tasks are moved to a remote server accessed through a radio link. The proposed system is based on a CMOS feature extraction chip for speech recognition that computes 15 cepstrum parameters, each 8 ms, and dissipates 30 mu W at 0.9-V supply. Single-cell battery operation is achieved. Processing relies on a novel feature extraction algorithm using 1-bit A/D conversion of the input speech signal. The chip has been implemented as a gate array in a standard 0.5-mu m, three-metal CMOS technology. The average energy required to process a single word of the TI46 speech corpus is 10 mu J. It achieves recognition rates over 98% in isolated-word speech recognition tasks.
引用
收藏
页码：1082 / 1089
页数：8
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