An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

被引：9

作者：

Chandrasekaran, Shrutisagar ^{[1
]}

Amira, Abbes ^{[1
]}

Shi Minghua ^{[2
]}

Bermak, Amine ^{[2
]}

机构：

[1] Brunel Univ, Sch Engn & Design, London, England

[2] Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong, Peoples R China

来源：

JOURNAL OF REAL-TIME IMAGE PROCESSING | 2008年 / 3卷 / 03期

关键词：

Finite Ridgelet Transform; Finite Radon Transform; Wavelets; FPGA; VLSI; ASIC; Image processing;

D O I：

10.1007/s11554-008-0081-1

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p(2)), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.

引用

页码：183 / 193

页数：11