An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

被引：9

作者：

Chandrasekaran, Shrutisagar ^{[1
]}

Amira, Abbes ^{[1
]}

Shi Minghua ^{[2
]}

Bermak, Amine ^{[2
]}

机构：

[1] Brunel Univ, Sch Engn & Design, London, England

[2] Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong, Peoples R China

来源：

JOURNAL OF REAL-TIME IMAGE PROCESSING | 2008年 / 3卷 / 03期

关键词：

Finite Ridgelet Transform; Finite Radon Transform; Wavelets; FPGA; VLSI; ASIC; Image processing;

D O I：

10.1007/s11554-008-0081-1

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p(2)), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.

引用

页码：183 / 193

页数：11

共 50 条

[1] An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform
Shrutisagar Chandrasekaran
Abbes Amira
Shi Minghua
Amine Bermak
Journal of Real-Time Image Processing, 2008, 3 : 183 - 193
[2] A VLSI architecture for finite ridgelet transform
Rahman, CA
Badawy, W
PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3, 2003, : 594 - 597
[3] Design and FPGA implementation of finite ridgelet transform
Uzun, IS
Amira, A
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 5826 - 5829
[4] An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation
Pandey, J. G.
Gurawa, Aanchal
Nehra, Heena
Karmakar, A.
2016 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURES, TECHNOLOGY AND APPLICATIONS (VLSI-SATA), 2016,
[5] An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation
Pandey, Jai Gopal
Goel, Tarun
Karmakar, Abhijit
VLSI DESIGN AND TEST, 2017, 711 : 270 - 278
[6] Resource-Efficient FPGA Architecture and Implementation of Hough Transform
Chen, Zhong-Ho
Su, Alvin W. Y.
Sun, Ming-Ting
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (08) : 1419 - 1428
[7] Efficient Architecture For Real Time Implementation of Hilbert Transform in FPGA
Prince, A. Amalin
Verma, Prakhar K.
Jayakumar, C.
Raju, Daniel
2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND COMMUNICATION TECHNOLOGIES, 2015,
[8] An efficient implementation of scalable architecture for discrete wavelet transform on FPGA
Guarisco, Michael
Zhang, Xun
Rabah, Hassan
Weber, Serge
2007 IEEE DALLAS/CAS WORKSHOP ON SYSTEM-ON-CHIP (SOC): DESIGN, APPLICATIONS, INTEGRATION, AND SOFTWARE, 2007, : 89 - +
[9] Design and implementation of a highly efficient VLSI architecture for discrete wavelet transform
Yu, C
Hsieh, CA
Chen, SJ
PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1997, : 237 - 240
[10] An Efficient FPGA and KBNN Based Training and Classification System for the Implementation of VLSI Architecture
Arunakumari, K.
Sheeba, I. Rexiline
PROCEEDINGS OF THE 2016 IEEE INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, SIGNAL PROCESSING AND NETWORKING (WISPNET), 2016, : 2493 - 2498

← 1 2 3 4 5 →