An improved transmission line pulsing (TLP) setup for electrostatic discharge (ESD) testing in semiconductor devices and ICs

被引：2

作者：

Lee, JC ^{[1
]}

Young, R ^{[1
]}

Liou, JJ ^{[1
]}

Croft, GD ^{[1
]}

Bernier, JC ^{[1
]}

机构：

[1] IBM Corp, RF Analog SiGe BiCMOS Device Modeling Grp, Burlington, VT USA

来源：

ICMTS 2001: PROCEEDINGS OF THE 2001 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES | 2001年

关键词：

D O I：

10.1109/ICMTS.2001.928668

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Transmission line pulsing (TLP) is a useful technique to characterize electrostatic discharge (ESD) events in semiconductor devices. The pulse waveforms generated by a typical TLP setup, however, are often distorted and oscillatory, In this paper, a new and simple experimental setup is developed to improve the shape of the TLP waveforms and thus to increase the effectiveness of the TLP technique. Experimental results obtained from the conventional and improved setups are presented and compared.

引用

页码：233 / 238

页数：6

共 5 条

[1]

Amerasekera A., 1995, ESD SILICON INTEGRAT

[2]

GOBNER H, 1999, EOS ESD S P, P19

[3] Modeling and measurement approaches for electrostatic discharge in semiconductor devices and ICs: an overview [J].

Lee, JC ;

Croft, GD ;

Liou, JJ ;

Young, WR ;

Bernier, J .

MICROELECTRONICS RELIABILITY, 1999, 39 (05) :579-593

[4] An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOS/ESD events [J].

Smith, JC .

ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS, 1999, 1999, :62-69

[5] Analyzing the switching behavior of ESD - Protection transistors by very fast transmission line pulsing [J].

Wolf, H ;

Gieser, H ;

Wilkening, W .

ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS, 1999, 1999, :28-37

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