A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation

被引：3

作者：

Feygin, G ^{[1
]}

Nagaraj, K ^{[1
]}

Chattopadhyay, R ^{[1
]}

Herrera, R ^{[1
]}

Papantonopoulos, I ^{[1
]}

Martin, D ^{[1
]}

Wu, P ^{[1
]}

Pavan, S ^{[1
]}

机构：

[1] Texas Instruments Inc, Warren, NJ USA

来源：

PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年

关键词：

D O I：

10.1109/CICC.2001.929745

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 8-bit AID converter using an efficient architecture is described. An important feature of this is a background offset cancellation scheme. This AID converter has been implemented in a 0.18 mum digital CMOS technology. It operates at up to 165 MS/s with an SNDR of 43.5 dB, a DNL of 0.7 LSB and an INL of 1 LSB. It occupies an active area of 0.9mm(2) and has a power dissipation of 140 mW.

引用

页码：153 / 156

页数：4

共 4 条

[1] A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist [J].