Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing

被引：10
|
作者：
Lisa, Nusrat Jahan [1 ]
Babu, Hafiz Md Hasan [2 ]
机构：
[1] Ahasnaullah Univ Sci & Technol, Dept Comp Sci & Engn, Dhaka, Bangladesh
[2] Univ Dhaka, Dept Comp Sci & Engn, Dhaka 1000, Bangladesh
来源：
2015 IEEE 45TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC | 2015年
关键词：
Quantum Computing; Quantum Logic; Ternary Peres Gate; Adder/Subtractor Circuit; Garbage Outputs; LOGIC;
D O I：
10.1109/ISMVL.2015.23
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we present an optimized design for the quantum ternary adder/subtractor circuit. We propose the design of quantum Ternary Peres Gate (TPG). The design of our proposed quantum ternary adder/subtractor circuit consists of two parts: a) Firstly, it has the design of a quantum ternary full-adder circuit using the proposed TPG gates; and b) Secondly, it designs the proposed adder/subtractor circuit by using the constructed full-adder in a) and M-S gates. We also propose a heuristic to design a compact ternary adder/subtractor circuit. Our circuits perform much better than the existing ones.
引用
收藏
页码：36 / 41
页数：6
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