Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing

In this paper, we present an optimized design for the quantum ternary adder/subtractor circuit. We propose the design of quantum Ternary Peres Gate (TPG). The design of our proposed quantum ternary adder/subtractor circuit consists of two parts: a) Firstly, it has the design of a quantum ternary full-adder circuit using the proposed TPG gates; and b) Secondly, it designs the proposed adder/subtractor circuit by using the constructed full-adder in a) and M-S gates. We also propose a heuristic to design a compact ternary adder/subtractor circuit. Our circuits perform much better than the existing ones.