Defects control in sub-quarter micron devices

被引:0
|
作者
Ikeda, K [1 ]
机构
[1] NEC Corp Ltd, ULSI Device Dev Labs, Kanagawa 2291198, Japan
来源
SILICON MATERIALS SCIENCE AND TECHNOLOGY, VOLS 1 AND 2 | 1998年
关键词
point defect; vacancy; interstitial Si; TED; implantation; plasma damage;
D O I
暂无
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
The key factors to fabricate sub-quarter micron devices are accurate control of dopant profiles and junction leakage current reduction The enhanced diffusion is strongly related with point defects such as interstitial Si and vacancy and the leakage current is related with residual defects, point defects and micro defects, which are not observed by TEM. Defects behavior clarification and control is important in low temperature process. In this paper,recent results on defect investigation and their control for ion implantation and plasma etching process are discussed. The influence of point defects is evaluated by positron annihilation, broadening of delta doped layer, Cu decoration and DLTS methods and device characteristics related with point defects is also discussed and then the method to minimize the influence is proposed.
引用
收藏
页码:1181 / 1195
页数:3
相关论文
共 50 条
  • [1] Polysilicon plug recess etch process for sub-quarter micron devices
    Kaplita, G
    Ranade, R
    Mathad, G
    PLASMA ETCHING PROCESSES FOR SUB-QUARTER MICRON DEVICES, PROCEEDINGS, 2000, 99 (30): : 213 - 219
  • [2] Junction profiles of sub keV ion implantation for deep sub-quarter micron devices
    Al-Bayati, A
    Tandon, S
    Doherty, R
    Murrell, A
    Wagner, D
    Foad, M
    Adibi, B
    Mickevicius, R
    Meniailenko, V
    Simeonov, S
    Jain, A
    Sing, D
    Ferguson, C
    Murto, R
    Larson, L
    2000 INTERNATIONAL CONFERENCE ON ION IMPLANTATION TECHNOLOGY, PROCEEDINGS, 2000, : 87 - 90
  • [3] Catadioptric systems for sub-quarter micron lithography
    Lee, KH
    Chung, HB
    Kim, DH
    Yoo, HJ
    17TH CONGRESS OF THE INTERNATIONAL COMMISSION FOR OPTICS: OPTICS FOR SCIENCE AND NEW TECHNOLOGY, PTS 1 AND 2, 1996, 2778 : 11 - 12
  • [4] STI process steps for sub-quarter micron CMOS
    Sallagoity, P
    Gaillard, F
    Rivoire, M
    Paoli, M
    Haond, M
    McClathie, S
    MICROELECTRONICS RELIABILITY, 1998, 38 (02) : 271 - 276
  • [5] Application of cobalt salicide in sub-quarter micron ULSI
    Bai, G
    Stivers, A
    SILICIDE THIN FILMS - FABRICATION, PROPERTIES, AND APPLICATIONS, 1996, 402 : 215 - 220
  • [6] Optimization of exposure procedures for sub-quarter micron CMOS applications
    Hotta, S
    Onozuka, T
    Fukumoto, K
    Shirai, S
    Okazaki, S
    OPTICAL MICROLITHOGRAPHY XI, 1998, 3334 : 598 - 606
  • [7] NEW NEGATIVE TONE RESISTS FOR SUB-QUARTER MICRON LITHOGRAPHY
    SACHDEV, H
    KWONG, R
    HUANG, W
    KATNANI, A
    SACHDEV, K
    MICROELECTRONIC ENGINEERING, 1995, 27 (1-4) : 393 - 396
  • [8] Sub-quarter micron contact hole fabrication using annular illumination
    Erdelyi, M
    Bor, Z
    Szabo, G
    Cavallaro, JR
    Smayling, MC
    Tittel, FK
    Wilson, WL
    OPTICAL MICROLITHOGRAPHY IX, 1996, 2726 : 88 - 93
  • [9] Sub-quarter micron silicon integrated circuits and single wafer processing
    Siagh, R
    MICROELECTRONICS RELIABILITY, 1998, 38 (09) : 1471 - 1483
  • [10] Sub-quarter micron silicon integrated circuits and single wafer processing
    Singh, R
    1997 21ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, VOLS 1 AND 2, 1997, : 19 - 24