Concurrent error detection in Reed-Solomon encoders and decoders

被引：13

作者：

Cardarilli, G. C. ^{[1
]}

Pontarelli, S. ^{[1
]}

Re, M. ^{[1
]}

Salsano, A. ^{[1
]}

机构：

[1] Univ Roma Tor Vergata, Dept Elect Engn, I-00133 Rome, Italy

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2007年 / 15卷 / 07期

关键词：

error correction coding; fault tolerance; Reed-Solomon codes;

D O I：

10.1109/TVLSI.2007.899241

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2(m)). These properties are related to the parity of the binary representation of the elements of the Galois Field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.

引用

页码：842 / 846

页数：5

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