MobileSP: An FPGA-Based Real-Time Keypoint Extraction Hardware Accelerator for Mobile VSLAM

被引:10
|
作者
Liu, Ye [1 ]
Li, Jingyuan [1 ]
Huang, Kun [1 ]
Li, Xiangting [1 ]
Qi, Xiuyuan [1 ]
Chang, Liang [2 ]
Long, Yu [1 ]
Zhou, Jun [1 ]
机构
[1] Univ Elect Sci & Technol China, Chengdu 611731, Sichuan, Peoples R China
[2] Univ Elect Sci & Technol China, Sch Informat & Commun Engn, Chengdu 611731, Sichuan, Peoples R China
基金
中国国家自然科学基金;
关键词
Feature extraction; Real-time systems; Decoding; Convolutional neural networks; Tensors; Field programmable gate arrays; Hardware acceleration; Keypoint extraction; CNN; FPGA; hardware accelerator; mobile VSLAM; ROBUST;
D O I
10.1109/TCSI.2022.3190300
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Keypoint extraction is a key technique for Visual Simultaneous Localization and Mapping (VSLAM). Recently, Convolutional Neural Network (CNN) has been used in the keypoint extraction for improving the accuracy. As one of the state-of-the-art CNN based keypoint extraction techniques, the SuperPoint ranked top in the CVPR2020 image matching challenge. However, the use of complex CNN makes it difficult to meet the real-time performance on a mobile platform with limited resource such as mobile robots and wearable Augmented Reality (AR) devices. In this work, based on the SuperPoint, we proposed an FPGA-based real-time keypoint extraction hardware accelerator through algorithm-hardware co-design for mobile VSLAM applications, which is named as MobileSP. Several algorithm and hardware level design techniques have been proposed to reduce the computation and improve the processing speed while maintaining high accuracy, including a partially shared detection & description encoding architecture, a pre-sorting based Non-Maximum Suppression (NMS) engine and a software-hardware hybrid pipeline computing technique. The design has been implemented and evaluated on a ZCU104 FPGA board. It achieves real-time performance of 42 fps with low Absolute Trajectory Error (ATE) of 1.82 cm simultaneously, outperforming several state-of-the-art designs.
引用
收藏
页码:4919 / 4929
页数:11
相关论文
共 50 条
  • [1] FPGA-Based Feature Extraction and Tracking Accelerator for Real-Time Visual SLAM
    Zhang, Jie
    Xiong, Shuai
    Liu, Cheng
    Geng, Yongchao
    Xiong, Wei
    Cheng, Song
    Hu, Fang
    SENSORS, 2023, 23 (19)
  • [2] An FPGA-based Parallel Hardware Architecture for Real-time Eye Detection
    Kim, Dongkyun
    Jung, Junhee
    Thuy Tuong Nguyen
    Kim, Daijin
    Kim, Munsang
    Kwon, Key Ho
    Jeon, Jae Wook
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2012, 12 (02) : 150 - 161
  • [3] A real-time SVM-based hardware accelerator for hyperspectral images classification in FPGA
    Martins, Lucas Amilton
    Viel, Felipe
    Seman, Laio Oriel
    Bezerra, Eduardo Augusto
    Zeferino, Cesar Albenes
    MICROPROCESSORS AND MICROSYSTEMS, 2024, 104
  • [4] An FPGA-Based High-Throughput Keypoint Detection Accelerator Using Convolutional Neural Network for Mobile Robot Applications
    Li, Jingyuan
    Liu, Ye
    Huang, Kun
    Zhou, Liang
    Chang, Liang
    Zhou, Jun
    2022 IEEE ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS AND ELECTRONICS, PRIMEASIA, 2022, : 81 - 84
  • [5] Real time Orthorectification by FPGA-based Hardware Acceleration
    Kuo, David
    Gordon, Don
    IMAGE AND SIGNAL PROCESSING FOR REMOTE SENSING XVI, 2010, 7830
  • [6] An FPGA-Based Hardware Accelerator for Real-Time Block-Matching and 3D Filtering
    Wang, Dong
    Xu, Jia
    Xu, Ke
    IEEE ACCESS, 2020, 8 : 121987 - 121998
  • [7] Real-Time Fixed-Point Hardware Accelerator of Convolutional Neural Network on FPGA Based
    Ozkilbac, Bahadir
    Ozbek, Ibrahim Yucel
    Karacali, Tevhit
    5TH INTERNATIONAL CONFERENCE ON COMPUTING AND INFORMATICS (ICCI 2022), 2022, : 1 - 5
  • [8] FPGA-based ORB Feature Extraction for Real-Time Visual SLAM
    Fang, Weikang
    Zhang, Yanjun
    Yu, Bo
    Liu, Shaoshan
    2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT), 2017, : 275 - 278
  • [9] A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded Real-Time Systems
    Tang, Yi
    Bergmann, Neil W.
    IEEE TRANSACTIONS ON COMPUTERS, 2015, 64 (05) : 1254 - 1267
  • [10] An FPGA-based Hardware Accelerator for Iris Segmentation
    Avey, Joe
    Jones, Phillip
    Zambreno, Joseph
    2018 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2018,