Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

被引:49
作者
Lee, Sung-Tae [1 ]
Lee, Jong-Ho [1 ]
机构
[1] Seoul Natl Univ, Dept Elect & Comp Engn, ISRC, Seoul, South Korea
基金
新加坡国家研究基金会;
关键词
neuromorphic; synaptic device; in-memory computing; NAND flash; deep neural networks; quantized neural networks; DEEP NEURAL-NETWORKS;
D O I
10.3389/fnins.2020.571292
中图分类号
Q189 [神经科学];
学科分类号
071006 ;
摘要
A novel operation scheme is proposed for high-density and highly robust neuromorphic computing based on NAND flash memory architecture. Analog input is represented with time-encoded input pulse by pulse width modulation (PWM) circuit, and 4-bit synaptic weight is represented with adjustable conductance of NAND cells. Pulse width modulation scheme for analog input value and proposed operation scheme is suitably applicable to the conventional NAND flash architecture to implement a neuromorphic system without additional change of memory architecture. Saturated current-voltage characteristic of NAND cells eliminates the effect of serial resistance of adjacent cells where a pass bias is applied in a synaptic string and IR drop of metal wire resistance. Multiply-accumulate (MAC) operation of 4-bit weight and width-modulated input can be performed in a single input step without additional logic operation. Furthermore, the effect of quantization training (QT) on the classification accuracy is investigated compared with post-training quantization (PTQ) with 4-bit weight. Lastly, a sufficiently low current variance of NAND cells obtained by the read-verify-write (RVW) scheme achieves satisfying accuracies of 98.14 and 89.6% for the MNIST and CIFAR10 images, respectively.
引用
收藏
页数:10
相关论文
共 31 条
[1]   YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration [J].
Andri, Renzo ;
Cavigelli, Lukas ;
Rossi, Davide ;
Benini, Luca .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (01) :48-60
[2]  
[Anonymous], 2019, IEDM
[3]  
[Anonymous], 2013, IEDM
[4]  
[Anonymous], 2020, IEEE CUST INTEGR CIR
[5]  
Choi J., 2019, P 2 SYSML C BOST FL
[6]   Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array [J].
Gao, Ligang ;
Chen, Pai-Yu ;
Yu, Shimeng .
IEEE ELECTRON DEVICE LETTERS, 2016, 37 (07) :870-873
[7]   Co-design of DNN Model Optimization for Binary ReRAM Array In-memory Processing [J].
Guan, Yue ;
Ohsawa, Takashi .
2019 IEEE 11TH INTERNATIONAL MEMORY WORKSHOP (IMW 2019), 2019, :32-35
[8]  
Hubara I., 2017, J MACH LEARN RES, V18, P6869
[9]  
Huh H., 2020, P IEEE INT SOL STAT, DOI [10.1109/ISSCC19947.2020.9063117, DOI 10.1109/ISSCC19947.2020.9063117]
[10]   Nanoscale Electronic Synapses Using Phase Change Devices [J].
Jackson, Bryan L. ;
Rajendran, Bipin ;
Corrado, Gregory S. ;
Breitwisch, Matthew ;
Burr, Geoffrey W. ;
Cheek, Roger ;
Gopalakrishnan, Kailash ;
Raoux, Simone ;
Rettner, Charles T. ;
Padilla, Alvaro ;
Schrott, Alex G. ;
Shenoy, Rohit S. ;
Kurdi, Buelent N. ;
Lam, Chung H. ;
Modha, Dharmendra S. .
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2013, 9 (02)