ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder

被引：0

作者：

Naik, Akhilesh ^{[1
]}

Deka, Debarshi ^{[1
]}

Pal, Dipankar ^{[1
]}

机构：

[1] BITS Pilani, Dept Elect & Elect Engn, KK Birla Goa Campus, Zuarinagar, India

来源：

2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS) | 2020年

关键词：

Square Root Carry Select Adder; Karatsuba Multiplier; Wallace-Tree-Multiplier; Dadda-Multiplier; Recursive Adaptive Karatsuba Algorithm;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Computation intensive applications such as DSP, image processing, floating point processors and communication technologies today require efficient binary multiplication which usually is the most power and time consuming block. This paper proposes an efficient design for unsigned binary multiplication to reduce delay. A 16x16-bit multiplier has been designed which is based on Vedic Karatsuba algorithm. It is optimized using adaptive and recursive approach combined with square-root-carry-select-adder. The designs have been coded in Verilog, synthesized in Cadence Genus and physically verified with Cadence Innovus in GDSII under ASIC platform.

引用

页数：4

共 26 条

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