Carbon nanotube vias: A reality check

This paper presents a comprehensive electrothermal analysis of single-walled (SWCNT) and multi-walled carbon nanotube (MWCNT) vias - possibly the most imminent application of CNT-based components in VLSI chips. Accurate resistance and thermal conductivity models are provided for isolated SWCNTs and MWCNTs, as well as bundles of these, based on detailed electrical and thermal transport physics in sub-pm regime. It is found that although CNT via resistance may not be a significant concern for local interconnects, the resistance must be minimized in order to avoid significant degradation of global interconnect performance. Furthermore, detailed three dimensional electrothermal simulations show that Joule heating and the presence of thermal contact resistance between CNTs and metal, can be major bottlenecks in extracting maximum thermal performance from ballistic CNT bundle vias. From a processing perspective, we show that the applicability of MWCNT vias, which are currently being fabricated, is severely limited by their thermal and electrical resistance. For SWCNT vias, small diameter CNTs with dense packing and good thermal and electrical contacts between CNT and metal are needed.