Warpage Improvement for Large Die Flip Chip Package

被引:6
作者
Xiong, Bingshou [1 ]
Lee, Myung-June [2 ]
Kao, Thomas [3 ]
机构
[1] Asia Pacific Pte Ltd, Xilinx, 5 Changi Business Pk Vista, Singapore 486040, Singapore
[2] Xilinx Inc, San Jose, CA 95124 USA
[3] Xilinx Taiwan, Taipei, Taiwan
来源
2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009) | 2009年
关键词
MECHANICAL-BEHAVIOR;
D O I
10.1109/EPTC.2009.5416574
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In the case of Field Programmable Gate Array (FPGA) chips, as the demand for higher speeds and enhanced functionality increases, the size of the flip chip die grows accordingly to offer higher number of logic cells. Large flip chip die also requires a large package for efficient signal routing. This paper shows a warpage improvement study including lid design and process optimization to solve warpage issue of large die FPGA flip chip packages with more fragile bump (23*23mm die and 42.5*42.5mm package). Though package warpage is well controlled for standard eutectic bump BOM (bill of materials) and process, it encountered problem when using higher Tg underfill, which is for better bump protection and reliability. A detailed finite element analysis was performed to simulate the effect of different lid structures (foot width, thickness etc) and lid materials (Cu, Al etc) on warpage. Actual units were built using improved lid structures and process. It was found that thicker Cu lid and lower underfill cure temperature are effective ways for warpage control, less than 8mils warpage was achieved by lid design and process optimization for this 42.5mm package with 23mm die with more fragile bump.
引用
收藏
页码:40 / +
页数:2
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