A 1.3-degree I/Q Phase Error, 7.1-8.7-GHz LO Generator with Single-Stage Digital Tuning Polyphase Filter

被引：3

作者：

Kodama, Hiroshi ^{[1
]}

Ishikawa, Hiromu ^{[1
]}

Oshima, Naoki ^{[1
]}

Tanaka, Akio ^{[1
]}

机构：

[1] NEC Corp Ltd, Kawasaki Ku, Kanagawa, Japan

来源：

2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2010年

关键词：

D O I：

10.1109/VLSIC.2010.5560318

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed an LO generator having 1) a digitally I/Q imbalance tuning polyphase filter and 2) a PLL with a varactor-based VCO and an interleaved charge pump for wide frequency operation. A 90-nm CMOS implementation showed that the equivalent maximum phase error was below 1.3 degrees in 7.1 - 8.7-GHz frequency range.

引用

页码：145 / 146

页数：2

共 8 条

[1] On the phase-noise and phase-error performances of multiphase LC CMOS VCOs [J].

Andreani, P ;

Wang, XY .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (11) :1883-1893

[2] A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration [J].

Berny, AD ;

Niknejad, AM ;

Meyer, RG .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (04) :909-917

[3]

*ECMA INT, 2008, ECMA368

[4]

MIRZAREI A, 2002, MWSCAS 2002 AUG, V3, P536

[5]

Sung Ho Wang, 2002, ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference, P807

[6]

TANAKA A, 2009, IEEE ISSCC FEB, P318

[7]

Windisch M, 2006, IEEE ICC, P257

[8] A new DC-offset and I/Q-mismatch compensation technique for a CMOS direct-conversion WLAN transmitter [J].

Yanagisawa, Kiyoshi ;

Matsuno, Noriaki ;

Maeda, Tadashi ;

Tanaka, Shinichi .

2007 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-6, 2007, :85-88

← 1 →