Multiple-gate CMOS thin-film transistor with polysilicon nanowire

被引：55

作者：

Im, Maesoon ^{[1
]}

Han, Jin-Woo ^{[1
]}

Lee, Hyunjin ^{[1
]}

Yu, Lee-Eun ^{[1
]}

Kim, Sungho ^{[1
]}

Kim, Chang-Hoon ^{[1
]}

Jeon, Sang Cheol ^{[2
]}

Kim, Kwang Hee ^{[2
]}

Lee, Gi Sung ^{[2
]}

Oh, Jae Sub ^{[2
]}

Park, Yun Chang ^{[2
]}

Lee, Hee Mok ^{[2
]}

Choi, Yang-Kyu ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Sch Elect Engn & Comp Sci, Div Elect Engn, Taejon 305701, South Korea

[2] Korea Natl NanoFab Ctr, Taejon 305806, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2008年 / 29卷 / 01期

关键词：

CMOS; multiple gate; nanoscale; nanowire; thin-film transistor (TFT); vertical integration;

D O I：

10.1109/LED.2007.911982

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.

引用

页码：102 / 105

页数：4

共 19 条

[1]

[Anonymous], P SOI C

[2] Low-temperature single-crystal Si TFT's fabricated on Si films processed via sequential lateral solidification [J].

Crowder, MA ;

Carey, PG ;

Smith, PM ;

Sposili, RS ;

Cho, HS ;

Im, JS .

IEEE ELECTRON DEVICE LETTERS, 1998, 19 (08) :306-308

[3] High-performance thin-film transistors fabricated using excimer laser processing and grain engineering [J].

Giust, GK ;

Sigmon, TW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (04) :925-932

[4]

Jung S.-M., 2006, IEDM Tech. Dig, P37

[5]

Jung SM, 2004, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, P265

[6] Short-channel amorphous-silicon thin-film transistors [J].

Kim, CD ;

Matsumura, M .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (12) :2172-2176

[7]

Lee H., 2006, VLSI TECH S, P70

[8] Fabrication of high-mobility p-channel poly-Si thin film transistors by self-aligned metal-induced lateral crystallization [J].

Lee, SW ;

Ihn, TH ;

Joo, SK .

IEEE ELECTRON DEVICE LETTERS, 1996, 17 (08) :407-409

[9] Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM's [J].

Miyamoto, S ;

Maegawa, S ;

Maeda, S ;

Ipposhi, T ;

Kuriyama, H ;

Nishimura, T ;

Tsubouchi, N .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (08) :1693-1698

[10] A proposed single grain-boundary thin-film transistor [J].

Oh, CH ;

Matsumura, M .

IEEE ELECTRON DEVICE LETTERS, 2001, 22 (01) :20-22

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