A supply noise insensitive PLL design through PWL behavioral modeling and simulation

被引：0

作者：

Lee, CH ^{[1
]}

McClellan, K

Choma, J

机构：

[1] Conexant Syst Inc, Wireless Commun Div, Newport Beach, CA 92660 USA

[2] Valence Semicond, Irvine, CA 92618 USA

[3] Univ So Calif, Dept Elect Engn Electrophys, Los Angeles, CA 90089 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2001年 / 48卷 / 12期

关键词：

behavioral modeling; phase-locked loop; piecewise linear;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a design flow for a supply noise insensitive (SNI) phase-locked loop (PLL). The influence on the PILL jitter of each noise component having high/low bandpass filter characteristics is investigated in the time domain. Acquisition time, tracking range, lock range and jitter are key parameters of a PLL system, and they are evaluated with piecewise linear (PWL) behavioral modeling. Finally, the SNI-PLL circuit having worst-case -45-dB power supply noise rejection based on the behavioral simulation results is implemented.

引用

页码：1137 / 1144

页数：8

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